The invention is based on a priority application EP 06300389.1 which is hereby incorporated by reference.
The present invention relates generally to serial data transmission using shift keying coded signals and more particularly to a data slicer circuit, a demodulation stage, a receiving system and a method for the reception of shift-keying coded data streams.
Serial data transmission is a generally known transmission technique used for the transmission of digital data, e.g. applicable in LAN or internet networks or mobile phone services. Depending on the transmission media i.e. electric, optical or radio, using wired or wireless connections, and to avoid undesired attenuation and signal interference effects, the digital signal to be transmitted is usually encoded by varying some parameters of a carrier signal, typically a sinusoidal signal, which is known as modulation. Basic well known digital modulation techniques for serial data transmission are amplitude-shift keying (ASK), frequency-shift keying (FSK) and phase-shift keying (PSK). FSK, for example, is a way of transmitting a data stream by changing the frequency of the carrier signal in accordance with the digital values of the data stream.
In a conventional digital communication system e.g. using FSK modulation, a receiving system has a demodulation stage DM, as shown in FIG. 1A, comprising a discriminator D capable of detecting (or discriminating between) the two frequencies of a baseband signal S, and producing an output voltage AF that is directly related to the frequency of the received signal. This is sometimes known as a frequency-to-voltage conversion. The output voltage signal AF of the discriminator, shown in FIG. 1B, provides values V1 and V0, where V1 is a voltage representative of the frequency f1 of the carrier signal for encoding a binary one and V0 is a voltage representative of the frequency f0 of the carrier signal for encoding a binary zero. There are numerous known techniques for providing a frequency-to-voltage conversion function, and the present invention is not intended to be limited to any such FM demodulation implementations.
Although the output voltage signal AF shown in FIG. 1B has been explained as having a substantially stable horizontal diagram characteristic with values V1 and V0 having substantially the same voltage, it is also possible that this output voltage signal AF presents non-horizontal diagram characteristic and/or non-stable phases and the values of V1 and VO be substantially different every bit.
The discriminator D is followed by a so-called data slicer DS, which receives the output voltage signal AF and provides a digital data stream output corresponding to the originally bit stream sent by the transmitter. The data slicer DS usually comprises a peak/valley detector or charge/discharge circuit connected to a comparator circuit which provides a binary one when the magnitude of the voltage output AF exceeds a slicing point, and a binary zero when said magnitude is below the slicing point. A known receiver system comprising a demodulation stage with the elements described above is disclosed in U.S. Patent Application 2004/0190650. Further, conventional receiving systems also comprise a power detector circuit PD which provides an indication RSSI, typically a DC voltage, of the baseband signal S strength at the input of the discriminator D. Low power intermediate frequency (IF) receiver circuit RX3141 for wireless radio serial data transmission using FSK modulation from HiMARK Technology, Inc. is also a known example of a conventional demodulation stage comprising the elements described above (a quadrature FM detector as discriminator, a charge/discharge circuitry and a 1-bit comparator as data slicer and which provides also an indication of the received signal strength RSSI at the input of the discriminator).
Although explained for a digital communications system using FSK modulation, the same principles apply for an ASK or PSK modulation in which the discriminator provides an output voltage AF that is directly related to the amplitude or the phase of the received signal.
A problem with the known type of serial data receiving systems is that the data slicer is not adequate for reception from the first bit, that is, a bit preamble prior to the data stream transmitted is needed in order to put the receiver into stable operation. This is needed in said prior art receiving systems in order to obtain an stable output voltage signal AF with stable absolute peak and valley voltage values and an stable average voltage value which is used as reference for the slicing comparator. Further, the data slicer of the known receiving systems is either designed for reception of continuous bit changes or for large strings of bits of the same polarity to avoid increase of errors due to noise.